Something to look forward to: As many consumers still get used to the differences between PCIe 3.0 and PCIe 4.0, and PCIe 5.0 SSDs begin to hit the market, the PCI-SIG consortium released specifications for PCIe 6.0 this week. For a long time, it doubled the bandwidth of PCIe 5.0.
Finally, the PCI-SIG consortium unveiled Specification 1.0 completes for PCIe 6.0 this week after reviewing several draft specs over the past few years. The last was in October.
The PCIe 6.0 specification will be backwards compatible with previous generations. The main advantage is that it doubles the data rate to 64 GT / s and doubles the maximum bandwidth to 256 GB / s on x16 lanes compared to PCIe 5.0. Other new features include four-level pulse amplitude modulation (PAM4), slight forward error correction (FEC), cyclic redundancy check (CRC) and flow control units (Flits).
According to the PCI-SIG FAQ, PAM4 is the one allow the specification to achieve such a high bandwidth. It modulates signals on four levels, packing two bits of information into a serial channel at the same time.
However, the increased bandwidth results in a higher bit error rate, which FEC and CRC should help correct. This bandwidth and these features require PCIe 6.0 to switch to data exchange in Flit mode.
The latest components in most consumer PCs today, such as graphics cards and SSDs, are still moving from PCIe 3.0 to 4.0, and some companies are starting to release their first 5.0 SSDs. PCI-SIG says version 6.0 will initially target data centers as well as industrial, automotive, military and aerospace applications. It probably won’t come to everyday consumers for a while.
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